Smaller integrated circuit geometries and advanced processing techniques have made it possible to achieve on-chip switching times of 120 ps to 250 ps per gate in CMOS integrated circuits. However, the signal handling capability of contemporary printed circuit boards and data processing systems is not on par with switching speeds of that order of magnitude, thus resulting in substantial signal degradation. Consequently, there is a critical need to develop techniques that will permit more effective interfacing of high-speed integrated circuits with printed circuit boards and ceramic or silicon substrates.
The proper driver matching impedance is derived from the drain current of the driver device. The drain current, I.sub.D, of a CMOS device is given approximately by the following equation: EQU I.sub.D =.mu..sub.o C.sub.o W/L [(V.sub.GS -V.sub.T)-(V.sub.DS /2)] V.sub.DS (1+.lambda..sub.VDS)
where
.mu..sub.o =surface mobility of the channel in cm.sup.2 /v-s; PA0 C.sub.o =capacitance per unit area of gate oxide; PA0 W=effective channel width; PA0 V.sub.GS =gate-to-source voltage; PA0 V.sub.T =threshold voltage; and PA0 .lambda..sub.VDS =the channel length modulation parameter. PA0 h=the height of the center of the wire over the ground plane, PA0 d=the diameter of the wire, and PA0 e.sub.r =the effective dielectric constant surrounding the wire. PA0 w=the width of the line, PA0 t=the thickness of the line, PA0 h=the height of the line from the ground plane, and PA0 e.sub.r =is effective dielectric constant of the medium between the line and the ground plane. PA0 w=the width of the strip line, PA0 h=the distance from the strip line to each of the ground planes, PA0 t=the thickness of the strip line, and PA0 e.sub.r = the relative dielectric constant of the board material. PA0 C.sub.D =the lumped capacitive load, and PA0 C.sub.O =the capacitance associated with the characteristic impedance.
The "on" resistance, R.sub.ON, is equal to the reciprocal of the partial derivative of the drain current with respect to the partial derivative of the drain-to-source voltage. That is: EQU R.sub.ON =(.alpha.I.sub.D /.alpha.V.sub.DS).sup.-1)
Since .alpha.I.sub.D /.alpha.V.sub.DS .apprxeq..mu..sub.o C.sub.o W/L [(V.sub.GS -V.sub.T)-(V.sub.DS /2)], R.sub.ON .apprxeq.L/.mu..sub.o C.sub.o W(V.sub.GS -V.sub.T) for small values of V.sub.DS.
A typical CMOS-to-printed circuit board (ceramic or silicon substrate) interface is illustrated in FIG. 1. In this graphic statement of the problem, the assumption is made that the transmission line is lightly loaded, having only a single lumped reactance Z1, consisting of a shunt resistor R1 and shunt capacitor C1. Capacitor C1 is considered to be associated with the combined capacitance of the receiver integrated circuit input capacitance and any additional stray capacitance at this junction. The resistance of resistor R1 is typically very high and may, therefore be ignored.
As the driver inputs 12 are driven from a low to high state, P-channel output driver transistor Q1 is operating initially in the saturation region, behaving as an ideal current source that delivers maximum current to the destination load and transmission line reactance. N-channel output driver transistor Q2, on the other hand, is initially in a turned-off state, behaving as an open circuit. As the voltage level on the gates of transistors Q1 and Q2 increases and the drain-to-source voltage decreases below the (V.sub.G S-V.sub.T) voltage, both devices begin to operate in their linear regions, where the R.sub.ON of each device remains nearly constant. While the devices operate in their linear regions, the transmission line is, in effect, terminated with a series termination resistance, R.sub.ON, the magnitude of which is matched to that of the transmission line. It is during this period when transistors Q1 and Q2 are operating in their linear regions (i.e., both devices are partially "on") that "crowbar" current will flow to ground. At the end of the low-to-high transition period, N-channel transistor Q2 becomes an ideal current source, tying the transmission line to ground, while P-channel transistor Q1 enters its high-resistance, turned-off state.
Matching the impedance of a driver circuit directly to that of the transmission line is preferable to using an unmatched driver interfaced to a transmission line having a series resistance termination consisting of either thin film resistors incorporated on the chip or within the package, or external resistors. This is so because, during transitions from low-to-high or high-to-low states, maximum drive current is available from the output driver. In comparison, when a series termination is used, suboptimal resistance choices are made as the designer attempts to maintain an acceptable level of drive current, while attempting to match transmission line impedance.
Characteristic impedance will be summarized for several types of transmission lines and various operating conditions. The R.sub.ON impedance of the N-channel and P-channel output driver transistors is optimally sized to match the given condition over the operating temperature range.
The characteristic impedance of a wire over a ground plane is given by the following formula: EQU Z.sub.O =(60/e.sub.r.sup.1/2)ln(4h/d)
where
The characteristic impedance of a microstrip line is given by the following formula: EQU Z.sub.O =[87/(e.sub.r +1.41).sup.1/2 ][ln(5.98h/0.8w+t)]
where
The characteristic impedance of strip line, on the other hand, is given by the following formula: EQU Z.sub.O =[60/e.sub.r.sup.1/2 ][ln[4(2h+t)/0.67.pi.w(0.8 +t/w)]]
where
The characteristic impedance of a microstrip or strip line modified by lumped capacitive loads is given by the following formula: EQU Z.sub.O =Z.sub.O /(1+C.sub.D /C.sub.O).sup.1/2
where
There are a number of problems associated with the creation of high-speed driver circuits. In order to match the impedance of a microstrip or stripline transmission line, a driver must be capable of high-current output to match the relatively high impedance of a microstrip or stripline transmission line. The high current required for impedance matching will likely result in the generation of high levels of crowbar current during the brief transition period when input shifts from low to high or high to low. If many devices within the circuit are simultaneously switching (a common occurrence in complex circuits), the crowbar current may well reach dangerously-high levels, thus overtaxing the power supply and resulting in unacceptably low voltage levels being delivered to the circuitry. In addition, since impedance is temperature related, a condition of matched impedance at one temperature will likely be a significant mismatch at another temperature.
A number of circuit designers have attempted to address the problems related to matching a driver circuit with the load. For example, in U.S. Pat. No. 4,414,480, which was issued in 1983 to John J. Zasio and is entitled "CMOS Circuit Using Transmission Line Interconnections", a CMOS driver circuit having impedance matched to the load is disclosed. However, this circuit ignores both the inevitable crowbar current effect and the effect of temperature on impedance. Another U.S. patent (U.S. Pat. No. 4,719,369) issued to Michio Asano, et al, and entitled "Output Circuit Having Transistor Monitor for Matching Output Impedance to Load Impedance", a CMOS driver circuit is disclosed which attempts to deal with the temperature effect on impedance. In this circuit, impedance is varied discontinuously, in order to approximate the impedance of the load, by means of a pair of analog-to-digital converters, each of which receives its input signal from a monitor MOSFET, the impedance of which varies with ambient temperature. Such an arrangement suffers from several drawbacks. First, the circuit is complex, relatively large, and subject to error in the high-noise environment of a high-speed digital circuit. The inventor states that his device is particularly useful for dealing with impedance variations due to variations in the manufacturing process. However, temperature variation plays a far more significant role in impedance variation within a CMOS driver circuit created with a well-controlled process. In fact, approximately ninety percent of the impedance variation is due to temperature. Like the circuit of the Zasio patent, the circuit of the Asano, et al, patent also ignores the crowbar current effect. Neither of the aforementioned patents makes mention of the need to match the combined transmission line and lumped parameter capacitive impedance. Although the lumped parameter capacitive loading is negligible for long transmission lines, it is particularly significant for transmission lines in the 2.5 cm to 15 cm range.